1. Field of Invention
This invention relates to communications systems. Specifically, the present invention relates systems for measuring and correcting error in reference frequency sources in cellular telecommunications systems.
2. Description of the Related Art
Cellular telecommunications systems are characterized by a plurality of mobile transceivers in communication with one or more base stations. Each transceiver includes a transmitter and a receiver. The receiver must often translate signals within a certain range of frequencies to a different range or band of frequencies. The accuracy of the frequency translation is affected by the accuracy of a periodic reference signal used in the translation. For example, in a code division multiple access (CDMA) cellular telephone network, a local oscillator in a mobile receiver provides a periodic signal that facilitates the translation of incoming radio frequency (RF) signals to an intermediate frequency (IF) band. If the frequency of the local oscillator is inaccurate, the translated signals may be translated outside of the desired IF band.
Digital telecommunications systems may employ one of several methods to demodulate a digitally modulated waveform. Such methods include binary-phase-shift-keying (BPSK), quadrature-phase-shift-keying (QPSK), offset QPSK (OQPSK), m-ary phase-shift-keying (MPSK), or quadrature amplitude modulation (QAM). It is often necessary for the system to lock to a received RF signal. The ability of the modulator to lock on the signal, and therefore its performance as indicated by the degradation in the measured bit error rate (BER) versus the theoretical BER, is influenced by the phase noise of the generated periodic reference signals.
Voltage-controlled temperature-compensated crystal oscillators (VC-TCXOs) often generate the periodic reference signals. A VC-TCXO has a control input used to adjust the frequency of the VC-TCXO in response to a high BER.
To measure the BER, a digital zero-crossing counter circuit is often used to perform error calculations on an IF output from the receiver. However, the counter circuit requires that the IF output signal drive digital circuitry in the zero-crossing circuit. This represents an inconvenience that increases system design time and expense. In addition, processing of high frequency IF signals requires fast digital circuitry that consumes excess power.
Alternatively, a digital signal processor calculates an error metric from digital baseband signals in the receiver. This system however, typically has limited accuracy and lock-in range.
Hence, a need exists in the art for an accurate, power-efficient system for measuring errors due to inaccurate reference frequencies. There is a further need for a system to compensate for the errors, the system having excellent error measurement accuracy and lock-in range.
The need in the art is addressed by the system for extracting and compensating for reference frequency error of the present invention. In the illustrative embodiment, the inventive system is adapted for use with a communications system and includes a frequency generator for outputting a reference signal of a first frequency. The frequency generator has a control input for adjusting the first frequency in response to a control signal. A receive circuit receives an input signal and provides an output signal having a first and second component in response thereto. An error extraction circuit provides an error value based on a phase difference between the first component and the second component, and provides the control signal in response thereto.
In a specific embodiment the frequency generator includes a voltage-controlled oscillator. The receive circuit is a telecommunications receiver that includes a vector demodulator. The vector demodulator produces in-phase and quadrature signals from the input signal. The in-phase and quadrature signals correspond to the first and second signal components, respectively. The error extraction circuit includes a positive error counting circuit for generating a positive count when the first component lags the second component. The error extraction circuit further includes a negative error counting circuit that generates a negative count when the first component leads the second component. The positive error counting circuit and the negative error counting circuit include first and second edge-triggered J-K flip-flops, respectively. A J-input of the second J-K flip-flop is connected in parallel to a clock input of the first J-K flip-flop, and a J-input of the first J-K flip-flop is connected to a clock input of the second J-K flip-flop. A K-input of the first J-K flip-flop and a K-input of the second J-K flip-flop are tied high.
In the illustrative embodiment, the error extraction circuit further includes an accumulation circuit for providing a difference of the positive count and the negative counts. The accumulation circuit includes an up-counter having an input connected to a Q-output of the first J-K flip-flop, and a down-counter having an input connected to a Q-output of the second J-K flip-flop. The accumulation circuit further includes a subtractor having an input connected, in parallel, to the output of the up-counter and the output of the down-counter. A frequency error control circuit generates the control signal from the difference of the positive count and the negative counts. The magnitude of the control signal is dependent on parameters of the frequency generator.